1. Field of the Invention
This invention relates to memory integrated circuits and, in particular, relates to multiport memory integrated circuits.
2. Discussion of the Related Art
In a high performance computer system, a dual-ported memory allows simultaneous memory access by, for example, both the central processor (CPU) and certain input and output (I/O) peripheral circuits. An example of such a computer system 100 is shown in FIG. 1. As shown in FIG. 1, computer system 100 comprises CPU 101, memory system 102, and I/O system 103. CPU 101 accesses memory system 102 via bus 104, and I/O system 103 accesses memory system 102 via bus 105. In computer system 100, both ports of a dual port memory are provided the same priority. Thus, when simultaneous memory accesses are pending at both ports, an arbitration circuit is necessary to resolve the order in which the memory is accessed. However, in many applications requiring a shared memory, e.g. in digital signal processors, certain devices often require immediate access on-demand. In those applications, a delay resulting from an existing memory access by another device, or due to latency in the arbitration circuit, may lose data unacceptably.
Various integrated circuit components have been designed to be used in a conventional memory array of a dual-port memory system. Such components include (i) QS7316 dual port random access memory (RAM), available from Quality Semiconductor Inc., Santa Clara, Calif.; (ii) M79018DX and M78004PX dual port RAMs, both available from AT&T Technologies Inc., Allentown, Pa., and (iii) various dual port SRAMs, e.g. IDT7133, from Integrated Device Technology, Inc., Santa Clara, Calif.
The QS7316 dual-port RAM referenced above is a clock-based dual port RAM supporting both random access and burst mode access from either or both ports. In the QS7316 dual-port RAM, neither port has a priority over the other port. However, the initial access latency in the QS7316 dual-port RAM is two to four clock cycles. The additional latency is required to synchronize accesses from both ports. Under burst mode, each port can be accessed every cycle after the initial access. The disadvantage of this component is the latency which is incurred when accessing either port.
The M79018DX and M78004PX components grant equal priority to the two ports of each component. Unlike the Q7316 integrated circuit, neither the M79018DX nor the M78004PX requires a clock signal input. However, in each of the M79018DX and the M78004PX components, memory access at one port can be held up for a long time period, while the memory access at the other port completes.
In the IDT7133 integrated circuit component, on-chip arbitration logic sets a busy flag to delay memory access by one of the ports, when simultaneous memory accesses from both ports occur. Under this scheme, memory access from either port may be blocked by the busy flag and be subject to an indefinite delay.